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[AK4125]
AK4125
192kHz / 24Bit High Performance Asynchronous SRC
GENERAL DESCRIPTION The AK4125 is a stereo digital sample rate converter (SRC). The input sample rate ranges from 8kHz to 216kHz. The output sample rate is from 8kHz to 216kHz. The system can take very simple configuration because the AK4125 has an internal PLL and does not need any master clock at slave mode. The AK4125 is suitable for the application interfacing to different sample rates such as high-end Car Audio and DVD recorder. FEATURES 1. SRC * Asynchronous Sample Rate Converter * Input Sample Rate Range (fsi): 8kHz 216kHz * Output Sample Rate Range (fso): 8kHz 216kHz * Input to Output Sample Rate Ratio: 1/6 to 6 * THD+N: -130dB * Dynamic Range: 140dB (A-weighted) * I/F format: MSB justified, LSB justified and I2S compatible * PLL for Internal Operation Clock * Clock for Master mode: 128/192/256/384/512/768fsi, 128/192/256/384/512/768fso * SRC Bypass mode * Soft Mute Function Power Supply * AVDD, DVDD: 3.0 3.6V (typ. 3.3V) Ta = -40 85C Package: 30pin VSOP AK4124 Pin-compatible
IDIF2 IDIF1 IDIF0 AVDD AVSS DVDD DVSS ODIF1 ODIF0 OBIT1 OBIT0 IBICK ILRCK SDTI Serial Audio I/F Serial Audio I/F OLRCK OBICK SDTO OMCLK PDN PLL2 PLL1 PLL0 SMUTE PLL DITHER
2. 3. 4. 5.
SRC
UNLOCK
IMCLK
CMODE2 CMODE1 CMODE0
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2007/07
[AK4125]
Ordering Guide
AK4125VF AKD4125 -40 +85C 30pin VSOP (0.65mm pitch) Evaluation Board for AK4125
Pin Layout
FILT AVSS PDN SMUTE DITHER PLL2 ILRCK IBICK SDTI IDIF0 IDIF1 IDIF2 PLL0 PLL1 UNLOCK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Top View
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AVDD DVSS DVDD OMCLK OLRCK OBICK SDTO ODIF1 ODIF0 CMODE2 CMODE1 CMODE0 IMCLK OBIT1 OBIT0
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[AK4125]
Compatibility with AK4124
Digital Filter Passband 0.985 FSO/FSI 6.000 0.905 FSO/FSI < 0.985 0.714 FSO/FSI < 0.905 0.656 FSO/FSI < 0.714 0.536 FSO/FSI < 0.656 0.492 FSO/FSI < 0.536 0.452 FSO/FSI < 0.492 0.357 FSO/FSI < 0.452 0.324 FSO/FSI < 0.357 0.246 FSO/FSI < 0.324 0.226 FSO/FSI < 0.246 0.1667 FSO/FSI < 0.226 AK4124 0.4583FSI 0.4167FSI 0.3195FSI 0.2852FSI 0.2182FSI 0.1982FSI 0.1740FSI 0.1212FSI 0.1072FSI 0.0595FSI 0.0484FSI 0.0182FSI AK4125 0.2177FSI 0.1948FSI 0.1458FSI 0.1302FSI 0.0917FSI 0.0826FSI 0.0583FSI
Refer to Table 8 for the detail of filter response.
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[AK4125]
PIN/FUNCTION
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Pin Name FILT AVSS PDN SMUTE DITHER PLL2 ILRCK IBICK SDTI IDIF0 IDIF1 IDIF2 PLL0 PLL1 UNLOCK OBIT0 OBIT1 IMCLK CMODE0 CMODE1 CMODE2 ODIF0 ODIF1 SDTO OBICK OLRCK OMCLK DVDD DVSS AVDD I/O O I I I I I/O I/O I I I I I I O I I I I I I I I O I/O I/O I Function PLL Loop Filter Pin Analog Ground Pin Power-Down Mode Pin "H": Power up, "L": Power down reset and initializes the control register. Soft Mute Pin "H" : Soft Mute, "L" : Normal Operation Dither Enable Pin "H" : Dither ON, "L" : Dither OFF PLL Mode Select 2 Pin Input Channel Clock Pin Audio Serial Data Clock Pin Audio Serial Data Input Pin Audio Interface Format 0 Pin for Input PORT Audio Interface Format 1 Pin for Input PORT Audio Interface Format 2 Pin for Input PORT PLL Mode Select 0 Pin PLL Mode Select 1 Pin Unlock Status Pin Bit Length Select 0 Pin for Output Data Bit Length Select 1 Pin for Output Data Master Clock Input Pin for Input PORT Clock Mode Select 0 Pin Clock Mode Select 1 Pin Clock Mode Select 2 Pin Audio Interface Format 0 Pin for Output PORT Audio Interface Format 1 Pin for Output PORT Audio Serial Data Output Pin for Output PORT Audio Serial Data Clock Pin for Output PORT Output Channel Clock Pin for Output PORT Master Clock Input Pin for Output PORT Digital Power Supply Pin, 3.0 3.6V Digital Ground Pin Analog Power Supply Pin, 3.0 3.6V
Note: All input pins must not be left floating.
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[AK4125]
Handling of Unused pins
The unused digital I/O pins should be processed appropriately as below. Classification Analog Digital Pin Name FILT SMUTE, DITHER IMCLK, OMCLK UNLOCK Setting This pin should be open. These pins should be connected to DVSS. These pins should be connected to DVSS in slave mode. This pin should be open.
ABSOLUTE MAXIMUM RATINGS
(AVSS, DVSS=0V; Note 1) Parameter Power Supplies: Analog Digital |AVSS - DVSS| (Note 2) Input Current, Any Pin Except Supplies Digital Input Voltage Ambient Temperature (Power applied) Storage Temperature Symbol AVDD DVDD GND IIN VIND Ta Tstg min -0.3 -0.3 -0.3 -40 -65 max 4.6 4.6 0.3 10 DVDD+0.3 85 150 Units V V V mA V C C
Note 1. All voltages with respect to ground. Note 2. AVSS and DVSS must be connected to the same ground. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (AVSS, DVSS=0V; Note 1) Parameter Symbol min typ Analog AVDD 3.0 3.3 Power Supplies Digital DVDD 3.0 3.3 (Note 3)
Note 1. All voltages with respect to ground. Note 3. The power up sequence between AVDD and DVDD is not important.
max 3.6 AVDD
Units V V
WARNING: AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet.
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[AK4125]
SRC CHARACTERISTICS (Ta=25C; AVDD=DVDD=3.3V; AVSS=DVSS=0V; Single Frequency = 1 kHz, data = 24bit; measurement bandwidth = 20Hz ~ FSO/2; unless otherwise specified.) Parameter Symbol min typ max Units SRC Characteristics: Resolution 24 Bits Input Sample Rate FSI 8 216 kHz Output Sample Rate FSO 8 216 kHz THD+N (Input = 1kHz, 0dBFS, Note 4) FSO/FSI = 44.1kHz/48kHz -130 dB FSO/FSI = 48kHz/44.1kHz -124 dB FSO/FSI = 48kHz/192kHz -133 dB FSO/FSI = 192kHz/48kHz -124 dB Worst Case (FSO/FSI = 32kHz/176.4kHz) -91 dB Dynamic Range (Input = 1kHz, -60dBFS, Note 4) FSO/FSI = 44.1kHz/48kHz 136 dB FSO/FSI = 48kHz/44.1kHz 136 dB FSO/FSI = 48kHz/192kHz 136 dB FSO/FSI = 192kHz/48kHz 132 dB Worst Case (FSO/FSI = 48kHz/32kHz) 132 dB Dynamic Range (Input = 1kHz, -60dBFS, A-weighted, Note 4) FSO/FSI = 44.1kHz/48kHz 140 dB Ratio between Input and Output Sample Rate FSO/FSI 1/6 6 Note 4. Measured by Audio Precision System Two Cascade.
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[AK4125]
FILTER CHARACTERISTICS
(Ta=25C; AVDD, DVDD=3.0 3.6V) Parameter Digital Filter Passband -0.01dB 0.985 FSO/FSI 6.000 0.905 FSO/FSI < 0.985 0.714 FSO/FSI < 0.905 0.656 FSO/FSI < 0.714 0.536 FSO/FSI < 0.656 0.492 FSO/FSI < 0.536 0.452 FSO/FSI < 0.492 0.357 FSO/FSI < 0.452 0.324 FSO/FSI < 0.357 0.246 FSO/FSI < 0.324 0.226 FSO/FSI < 0.246 0.1667 FSO/FSI < 0.226 Stopband 0.985 FSO/FSI 6.000 0.905 FSO/FSI < 0.985 0.714 FSO/FSI < 0.905 0.656 FSO/FSI < 0.714 0.536 FSO/FSI < 0.656 0.492 FSO/FSI < 0.536 0.452 FSO/FSI < 0.492 0.357 FSO/FSI < 0.452 0.324 FSO/FSI < 0.357 0.246 FSO/FSI < 0.324 0.226 FSO/FSI < 0.246 0.1667 FSO/FSI < 0.226 Passband Ripple Stopband 0.985 FSO/FSI 6.000 Attenuation 0.905 FSO/FSI < 0.985 0.714 FSO/FSI < 0.905 0.656 FSO/FSI < 0.714 0.536 FSO/FSI < 0.656 0.492 FSO/FSI < 0.536 0.452 FSO/FSI < 0.492 0.357 FSO/FSI < 0.452 0.324 FSO/FSI < 0.357 0.246 FSO/FSI < 0.324 0.226 FSO/FSI < 0.246 0.1667 FSO/FSI < 0.226 Group Delay (Note 5) Symbol PB PB PB PB PB PB PB PB PB PB PB PB SB SB SB SB SB SB SB SB SB SB SB SB PR SA SA SA SA SA SA SA SA SA SA SA SA GD min 0 0 0 0 0 0 0 0 0 0 0 0 0.5417FSI 0.5021FSI 0.3965FSI 0.3643FSI 0.2974FSI 0.2813FSI 0.2604FSI 0.2116FSI 0.1969FSI 0.1573FSI 0.1471FSI 0.1020FSI 121.2 121.4 115.3 116.9 114.6 100.2 103.3 102.0 103.6 104.0 103.3 73.2 typ max 0.4583FSI 0.4167FSI 0.3195FSI 0.2852FSI 0.2182FSI 0.2177FSI 0.1948FSI 0.1458FSI 0.1302FSI 0.0917FSI 0.0826FSI 0.0583FSI Units kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz dB dB dB dB dB dB dB dB dB dB dB dB dB 1/fs
0.01
56
-
Note 5. This delay is the a period from the rising edge of ILRCK, just after the data is input, to the rising edge of OLRCK, just after the data is output, when there is no phase difference between ILRCK and OLRCK.
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[AK4125]
DC CHARACTERISTICS
(Ta=25C; AVDD, DVDD=3.0 3.6V) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage (Iout=-400A) Low-Level Output Voltage (Iout=400A) Input Leakage Current Symbol VIH VIL VOH VOL Iin min 70%DVDD DVDD-0.4 typ max 30%DVDD 0.4 10 Units V V V V A
Power Supplies Power Supply Current Normal operation (PDN pin = "H") FSI=FSO=48kHz at Slave Mode: AVDD=DVDD=3.3V FSI=FSO=192kHz at Master Mode: AVDD=DVDD=3.3V : AVDD=DVDD=3.6V Power down (PDN pin = "L") (Note 6) AVDD+DVDD Note 6. All digital input pins are held DVSS.
13 55 85 10 100
mA mA mA A
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[AK4125]
SWITCHING CHARACTERISTICS (Ta=25C; AVDD, DVDD=3.0 3.6V; CL=20pF) Parameter Symbol min Master Clock Timing Frequency fCLK 1.024 Pulse Width Low tCLKL 0.4/fCLK Pulse Width High tCLKH 0.4/fCLK LRCK for Input data (ILRCK) Frequency fs 8 Duty Cycle Slave Mode Duty 48 Master Mode Duty LRCK for Output data (OLRCK) Frequency fs 8 Duty Cycle Slave Mode Duty 48 Master Mode Duty Audio Interface Timing Input PORT (Slave mode) 1/128fs tBCK IBICK Period (8kHz 108kHz) 1/64fs tBCK (108kHz 216kHz) 27 tBCKL IBICK Pulse Width Low 27 tBCKH Pulse Width High 15 tLRB ILRCK Edge to IBICK "" (Note 7) 15 tBLR IBICK "" to ILRCK Edge (Note 7) 15 tSDH SDTI Hold Time from IBICK "" 15 tSDS SDTI Setup Time to IBICK "" Input PORT (Master mode) IBICK Frequency fBCK IBICK Duty dBCK IBICK "" to ILRCK tMBLR -20 SDTI Hold Time from IBICK "" tSDH 15 SDTI Setup Time to IBICK "" tSDS 15 Output PORT (Slave mode) 1/128fs tBCK OBICK Period (8kHz 108kHz) 1/64fs tBCK (108kHz 216kHz) 27 tBCKL OBICK Pulse Width Low 27 tBCKH Pulse Width High 20 tLRB OLRCK Edge to OBICK "" (Note 7) 20 tBLR OBICK "" to OLRCK Edge (Note 7) 2 tLRS OLRCK to SDTO (MSB) (Except I S mode) tBSD OBICK "" to SDTO Output PORT (Master mode) OBICK Frequency fBCK OBICK Duty dBCK OBICK "" to OLRCK tMBLR -20 OBICK "" to SDTO tBSD -20 Reset Timing PDN Pulse Width (Note 8) tPD 150 Note 7. BICK rising edge must not occur at the same time as LRCK edge. Note 8. The AK4125 can be reset by bringing the PDN pin = "L".
typ
max 41.472
Units MHz ns ns kHz % % kHz % %
50 50
216 52
50 50
216 52
ns ns ns ns ns ns ns ns 64fs 50 20 Hz % ns ns ns ns ns ns ns ns ns ns ns Hz % ns ns ns
20 20 64fs 50 20 20
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[AK4125]
Timing Diagram
1/fCLK VIH MCLK VIL tCLKH 1/fs VIH LRCK VIL tBCK VIH BICK VIL tBCKH tBCKL
Clock Timing
VIH LRCK VIL tBLR tLRB VIH BICK VIL tLRS tBSD
tCLKL
SDTO tSDS tSDH
50%DVDD
VIH SDTI VIL
Audio Interface Timing (Slave mode) Note: BICK shows IBICK and OBICK, LRCK shows ILRCK and OLRCK.
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[AK4125]
LRCK
50%DVDD
tMBLR
dBCK 50%DVDD
BICK
tBSD
SDTO tSDS tSDH
50%DVDD
VIH SDTI VIL
Audio Interface Timing (Master mode) Note: BICK shows IBICK and OBICK, LRCK shows ILRCK and OLRCK.
tPD PDN VIL
Power Down & Reset Timing
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[AK4125]
OPERATION OVERVIEW
System Clock & Audio Interface Format for Input PORT
The input port works in master mode or slave mode. An internal system clock is created by the internal PLL using ILRCK (Mode 0 2 of Table 2) or IBICK (Mode 4 7 of Table 2) in slave mode. The MCLK is not needed in slave mode. And an internal system clock is created by IMCLK (Mode 8 15 of Table 2) in master mode. The PLL2-0 pins and IDIF2-0 pins select the master/slave and PLL mode. The PLL2-0 pins and IDIF2-0 pins should be controlled when the PDN pin = "L". The IDIF2-0 pins select the audio interface format for the input port. The audio data is MSB first, 2's compliment format. The SDTI is latched on the rising edge of IBICK. Select the audio interface format when the PDN pin = "L". When in BYPASS mode, both IBICK and OBICK are fixed to 64fs. Mode 0 1 2 3 4 5 6 7 IDIF2 L L L L H H H H IDIF1 L L H H L L H H IDIF0 SDTI Format ILRCK IBICK IBICK Freq L 16bit, LSB justified 32fsi H 20bit, LSB justified 40fsi Input Input L 24/20bit, MSB justified 48fsi 2 H 24/16bit, I S Compatible 48fsi or 32fsi L 24bit, LSB justified 48fsi H 24bit, MSB justified 64fs Output Output L 24bit, I2S Compatible 64fs H Reserved Table 1. Input Audio Interface Format (Input PORT) PLL2 L L Slave IMCLK = DVSS IBICK = Input ILRCK = Input L L H H H H L L L L H H H H PLL1 L L H PLL0 L H L ILRCK Freq 8k 96kHz 8k 216kHz 16k 216kHz (Note 9) IBICK Freq Depending on IDIF2-0 (Note 10) Master / Slave
Slave
Master
Mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Master / Slave
IMCLK Not needed. (Note 12)
SMUTE (Note 13) Manual
Semi-Auto
Master IMCLK = Input IBICK = Output ILRCK = Output
H H Reserved L L 32fsi (Note 11) Not L H 64fsi 8k 216kHz needed. (Note 10) H L 128fsi (Note 12) 64fsi H H L L 128fs 8k 216kHz L H 256fs 8k 108kHz H L 512fs 8k 54kHz H H 128fs 8k 216kHz 64fs L L 192fs 8k 216kHz L H 384fs 8k 108kHz H L 768fs 8k 54kHz H H 192fs 8k 216kHz Table 2. PLL Setting (Input PORT)
Manual
Semi-Auto
Manual
Semi-Auto
Manual
Semi-Auto
Note 9. PLL lock rage is changed by the value of R and C connected FILT pin. Refer to "PLL Loop Filter". Note 10. IBCIK must be continuous except when the clocks are changed. Note 11. IBCIK = 32fsi is supported only 16bit LSB justified and I2S Compatible. Note 12. Fixed to DVSS. Note 13. Refer to "Soft Mute Operation" for Manual mode and Semi-Auto mode.
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[AK4125]
ILRCK
0123 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1
IBICK(32fs) SDTI(i) IBICK(64fs) SDTI(i)
Don't Care 15:MSB, 0:LSB Lch Data Rch Data 15 14 13 12 10 Don't Care 15 14 13 12 210 15 14 13 0123 7 6 5 4 3 2 1 0 15 14 13 17 18 19 20 31 0 1 2 3 7 6 5 4 3 2 1 0 15 17 18 19 20 31 0 1
Figure 1. Mode 0 Timing
ILRCK
012 12 13 24 31 0 1 2 12 13 24 31 0 1
IBICK(64fs) SDTI(i)
Don't Care 19:MSB, 0:LSB Lch Data Rch Data 19 8 10 Don't Care 19 8 10
Figure 2. Mode 1 Timing
ILRCK
012 20 21 22 23 24 31 0 1 2 20 21 22 23 24 31 0 1
IBICK(64fs) SDTI(i)
23 22 43210 Don't Care 23 22 43210 Don't Care 23
23:MSB, 0:LSB Lch Data Rch Data
Figure 3. Mode 2,5 Timing (24bit MSB)
ILRCK
0123 21 22 23 24 25 012 21 22 23 24 25 01
IBICK(64fs) SDTI(i)
23 22 43210 Don't Care 23 22 43210 Don't Care
23:MSB, 0:LSB Lch Data Rch Data
2
Figure 4. Mode 3, 6 Timing (24bit I S)
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[AK4125]
ILRCK
012 89 24 31 0 1 2 89 24 31 0 1
IBICK(64fs) SDTI(i)
Don't Care 23:MSB, 0:LSB Lch Data Rch Data 23 8 10 Don't Care 23 8 10
Figure 5. Mode 4 Timing
System Clock & Audio Interface Format for Output PORT
The output port works in master mode or slave mode. The MCLK is not needed in slave mode. The CMODE2-0 pins select the master/slave and bypass mode. The CMODE2-0 pins should be controlled when the PDN pin = "L". The ODIF1-0 pins and OBIT1-0 pins select the audio interface format for the output port. The audio data is MSB first, 2's compliment format. The SDTO is clocked out on the falling edge of OBICK. Select the audio interface format when the PDN pin = "L". When in BYPASS mode, both IBICK and OBICK are fixed to 64fs. Mode 0 1 2 3 4 5 6 7 CMODE 2 L L L L H H H H CMODE CMODE0 Master / Slave OMCLK 1 L L Master 256fso L H Master 384fso H L Master 512fso H H Master 768fso L L Slave Not used. Set to DVSS. L H Master 128fso H L Master 192fso H H Master (Bypass) Not used. Set to DVSS. Table 3. Master/Slave Control (Output PORT) Mode ODIF1 ODIF0 SDTO Format 0 L L LSB justified 1 L H (Reserved) 2 H L MSB justified 3 H H I2S Compatible Table 4. Output Audio Interface Format 1 (Output PORT) Mode 0 1 2 3 4 5 6 7 Master / Slave Slave CMODE2-0 = "HLL" Master Except CMODE2-0 = "HLL" OBIT1 OBIT0 SDTO OLRCK OBICK OBICK Frequency MSB justified, I2S LSB justified 32fso 36fso 64fso 40fso 48fso 64fso fso 8k 108kHz 8k 108kHz 8k 54kHz 8k 54kHz 8k 216kHz 8k 216kHz 8k 216kHz 8k 216kHz
L L 16bit L H 18bit Input Input H L 20bit H H 24bit L L 16bit L H 18bit Output Output H L 20bit H H 24bit Table 5. Output Audio Interface Format 2 (Output PORT)
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[AK4125]
OLRCK
01 8 9 10 11 12 13 14 15 16 17 20 21 22 23 29 30 31 0 1 8 9 10 11 12 13 14 15 16 17 20 21 22 23 29 30 31 0 1 2
OBICK(64fs) SDTO(O)
15:MSB, 0:LSB 15 14 11 10 9 8 210 15 14 11 10 9 8 210
SDTO(O)
17:MSB, 0:LSB
17 16 15 14
11 10 9 8
210
17 16 15 14
11 10 9 8
210
SDTO(O) SDTO(O)
19 18 17 16 15 14 19:MSB, 0:LSB 23 22 21 20 19 18 17 16 15 14 23:MSB, 0:LSB Lch Data
11 10 9 8
210
19 18 17 16 15 14
11 10 9 8
210
11 10 9 8
210
23 22 21 20 19 18 17 16 15 14
11 10 9 8
210
Rch Data
Figure 6. LSB Timing
OLRCK
01234 13 14 15 16 17 18 19 20 21 22 23 24 31 0 1 2 3 4 13 14 15 16 17 18 19 20 21 22 23 24 31 0 1 2
OBICK(64fs) SDTO(O) SDTO(O) SDTO(O) SDTO(O)
15 14 13 12 210 15:MSB, 0:LSB 17 16 15 14 43210 17:MSB, 0:LSB 19 18 17 16 6543210 19:MSB, 0:LSB 23 22 21 20 10 9 8 7 6 5 4 3 2 1 0 23:MSB, 0:LSB Lch Data Rch Data 23 22 21 20 10 9 8 7 6 5 4 3 2 1 0 23 22 19 18 17 16 6543210 19 18 17 16 15 14 43210 17 16 15 14 13 12 210 15 14
Figure 7. MSB Timing
OLRCK
01234 14 15 16 17 18 19 20 21 22 23 24 01234 14 15 16 17 18 19 20 21 22 23 24 31 0 1 2
OBICK(64fs) SDTO(O) SDTO(O) SDTO(O) SDTO(O)
15 14 13 12 210 15:MSB, 0:LSB 17 16 15 14 43210 17:MSB, 0:LSB 19 18 17 16 6543210 19:MSB, 0:LSB 23 22 21 20 10 9 8 7 6 5 4 3 2 1 0 23:MSB, 0:LSB Lch Data Rch Data
2
15 14 13 12
210
15
17 16 15 14
43210
17
19 18 17 16
6543210
19
23 22 21 20
10 9 8 7 6 5 4 3 2 1 0
23
Figure 8. I S Compatible Timing
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[AK4125]
Soft Mute Operation
1. Manual mode Soft mute operation is performed in the digital domain of the SRC output. Soft mute can be controlled by the SMUTE pin. When the SMUTE pin changes to "H", the SRC output data is attenuated by - within 1024 OLRCK cycles. When the SMUTE pin changes to "L", the mute is cancelled and the output attenuation gradually changes to 0dB during 1024 OLRCK cycles. If the soft mute is cancelled before mute state after starting the operation, the attenuation is discontinued and returned to 0dB by the same cycles. The soft mute is effective for changing the signal source.
SM UTE 1024/fso 0dB A ttenuation (1) (2)
-
SDTO
Figure 9. Soft Mute Function (Manual Mode) (1) The output data is attenuated by - during 1024 OLRCK cycles (1024/fso). (2) If the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to 0dB by the same number of clock cycles. 2. Semi-Auto mode The soft mute is cancelled automatically by the setting of PLL2-0 pins (Table 2), after the AK4125 detects the rising edge (PDN pin = "L" "H") and the mute is continued during 4410/fso=100ms@fso=44.1kHz. After PDN pin = "L" "H" and when the SMUTE pin is "H", the mute is not cancelled.
P D N pin
"L"
S M U TE pin
D on't care
"L"
0dB A ttenuation
(1) 4410/fso
-
S D TO
Figure 10. Soft Mute Function (Semi-Auto Mode) (1) The output data is returned to 0dB during 1024 OLRCK cycles (1024/fso).
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[AK4125]
Dither
The AK4125 has a dither circuit. The dither circuit adds the dither to the LSB of the output data, which is the value of the OBIT1-0 pins, by DITHER pin = "H" regardless of the SRC mode or the SRC bypass mode.
System Reset
Bringing the PDN pin = "L" sets the AK4125 power-down mode and initializes the digital filter. The AK4125 should be reset once by bringing the PDN pin = "L" when power-up. When the PDN pin = "L", the SDTO output is "L". The SDTO valid time is 100ms. Until the output data becomes valid, the SDTO pin outputs "L".
Case 1
External clocks (Input port) SDTI External clocks (Output port) PDN
< 100ms
Don't care Don't care Don't care
Input Clocks 1 Input Data 1 Output Clocks 1
Input Clocks 2 Input Data 2 Output Clocks 2
Don't care Don't care Don't care
< 100ms
Normal operation PD PLL lock & fs detection Normal operation
(Internal state) Power-down SDTO
PLL lock & fs detection
Power-down
"0" data
Normal data
"0" data
Normal data
"0" data
UNLOCK
Figure 11. System Reset
Case 2
External clocks (Input port) SDTI External clocks (Output port) PDN
< 100ms PLL lock & fs detection Normal operation
(No Clock) (Don't care) (Don't care)
Input Clocks Input Data Output Clocks
Don't care Don't care Don't care
(Internal state) Power-down
PLL Unlock
Power-down
SDTO
"0" data
Normal data
"0" data
UNLOCK
Figure 12. System Reset 2
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[AK4125]
Internal Reset Function for Clock Change
The AK4125 is reset automatically when the output clock is stopped. If the output clock is started again, normal data is output within 100ms.
Sequence of Changing Clocks
The change of the clock supplied to AK4125 is shown in Figure 13.
External clocks (Input port or Output port) PDN pin
< 100ms
Clocks 1
Don't care
Clocks 2
(Internal state) Normal operation Power-down PLL lock &
Note1
fs detection
Normal operation
SDTO SMUTE (Note2, recommended) Att.Level 0dB -dB
Normal data
Normal data 1024/fso
1024/fso
Figure 13. Sequence of changing clocks Note 1. The data on SDTO may cause a clicking noise. To prevent this, set "0" to the SDTI from GD before the PDN pin changes to "L". It makes the data on SDTO remain as "0". Note 2. SMUTE can also remove the unknown data.
UNLOCK pin
The UNLOCK pin outputs "L" when the internal PLL is locked. When the internal PLL is unlocked, the UNLOCK pin outputs "H" and the SDTO = "0". When the PDN pin = "L", the UNLOCK pin outputs "H".
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[AK4125]
PLL Loop Filter
The C1 and R should be connected in series and attached between FILT pin and AVSS in parallel with C2. (Figure 14, Table 6, Table 7) Please be careful the noise onto the FILT pin. When using IBICK, the value of external element is not dependent on the IBICK input frequency.
AK4125
FILT R C1 AVSS
C2
Figure 14. PLL Loop Filter [Input PORT in slave mode] 1. When using ILRCK PLL2 L L L PLL1 L L H PLL0 L ILRCK R [] 8k 96kHz 1.8k 5% 8k 216kHz 1k 5% H 16k 216kHz 1.5k 5% 8k 216kHz 1k 5% L 16k 216kHz 1.5k 5% Table 6. PLL Loop Filter (ILRCK Mode) C1 [F] 0.68 30% 1.0 30% 0.68 30% 1.0 30% 0.68 30% C2 [nF] 0.68 30% 2.2 30% 0.68 30% 2.2 30% 0.68 30%
- Note. Smaller value can be selected for the capacitors (C1, C2) in case of ILRCK range from 16kHz to 216kHz.. 2. When using IBICK PLL2 H PLL1 * PLL0 ILRCK R [] C1 [F] * 8k 216kHz 470 5% 0.22 30% Table 7. PLL Loop Filter (IBICK Mode, *: Don't care) C2 [nF] 1.0 30%
Note. The IBCIK must be continuous except when the clocks are changed. Note. IBCIK = 32fsi is supported only 16bit LSB justified and I2S Compatible. [Input PORT in master mode] 1. When IMCLK is 256fs, 384fs, 512fs or 768fs, any external parts shown in Figure 14 are not required. 2. When IMCLK is 128fs or 192fs, the external parts shown in Table 7 are required.
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[AK4125]
SYSTEM DESIGN
Figure 15, Figure 16 show the system connection diagram. The evaluation board demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. * Input PORT: Slave Mode, IBICK lock mode (64fsi), 24bit MSB justified * Output PORT: Slave mode, 24bit MSB justified * Dither = OFF
470 1.0n 1 FILT 0.22 2 AVSS Reset 3 PDN 4 SMUTE 5 DITHER 6 PLL2 fsi 64fsi 7 ILRCK 8 IBICK 9 SDTI 10 IDIF0 11 IDIF1 12 IDIF2 13 PLL0 14 PLL1 15 UNLOCK DVSS 29 DVDD 28 OMCLK 27 OLRCK 26 OBICK 25 0.1 AVDD 30 0.1
10
Supply 3.0 ~ 3.6V
fso 64fso DSP
AK4125
SDTO 24 ODIF1 23 ODIF0 22 CMODE2 21 CMODE1 20 CMODE0 19 IMCLK 18 OBIT1 17 OBIT0 16
DSP, uP
Note: - AVSS and DVSS of the AK4125 should be distributed separately from the ground of external digital devices (MPU, DSP etc.). - All digital input pins should not be left floating. Figure 15. Typical Connection Diagram (Slave mode)
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[AK4125]
* Input PORT: Slave Mode, IBICK lock mode (64fsi), 24bit MSB justified * Output PORT: Master mode, 24bit MSB justified * Dither = OFF
470 1.0n 1 FILT 0.22 2 AVSS Reset 3 PDN 4 SMUTE 5 DITHER 6 PLL2 fsi 64fsi 7 ILRCK 8 IBICK 9 SDTI DSP, uP 10 IDIF0 11 IDIF1 12 IDIF2 13 PLL0 14 PLL1 15 UNLOCK CMODE2 21 CMODE1 20 CMODE0 19 IMCLK 18 OBIT1 17 OBIT0 16 DVSS 29 DVDD 28 OMCLK 27 OLRCK 26 OBICK 25 0.1 AVDD 30 0.1
10
Supply 3.0 ~ 3.6V
128fso fso 64fso DSP
AK4125
SDTO 24 ODIF1 23 ODIF0 22
Note: - AVSS and DVSS of the AK4125 should be distributed separately from the ground of external digital devices (MPU, DSP etc.). - All digital input pins should not be left floating. Figure 16. Typical Connection Diagram (Master mode)
1. Grounding and Power Supply Decoupling
The AK4125 requires careful attention to power supply and grounding arrangements. Alternatively if AVDD and DVDD are supplied separately, the power up sequence is not important. Decoupling capacitors should be as near to the AK4125 as possible, with the small value ceramic capacitor being the nearest.
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[AK4125]
2. Jitter Tolerance
Figure 17 shows the jitter tolerance to ILRCK and IBICK. The jitter quantity is defined by the jitter frequency and the jitter amplitude shown in Figure 17. When the jitter amplitude is 0.01Uipp or less, the AK4125 operates normally regardless of the jitter frequency.
AK4125 Jitter Tolerance
10.00
1.00 Amplitude [UIpp]
(3)
0.10
(2)
0.01
(1)
0.00 1 10 100 Jitter Frequency [Hz] 1000 10000
(1) Normal operation (2) There is a possibility that the distortion degrades. (It may degrade up to about -50dB.) (3) There is a possibility that the output data is lost. Note: - When PLL2-0 = "L/L/L", "L/L/H", "L/H/L", the jitter amplitude is for ILRCK and 1UI (Unit Interval) is one cycle of ILRCK. When FSI = 48kHz, 1UI is 1/48kHz = 20.8s. - When PLL2-0 = "H/*/*" (*: Don't care), the jitter amplitude is for IBICK and 1UI (Unit Interval) is one cycle of IBICK. When FSI = 48kHz, 1UI is 1/(64 x 48kHz) = 326ns. Figure 17. Jitter Tolerance
Tracking to the Input Sampling Frequency
When the ILRCK is generated by an external PLL, it may take time to settle after changing the input sampling frequency because the response of an external PLL to the frequency change is slow. The AK4125 operates normally up to 23%/sec speed but outputs incorrect data at the speed of the frequency change over 23%/sec.
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[AK4125]
3. Digital Filter Response Example
Table 8 shows the examples of digital filter response performed by the AK4125. Ratio 4.000 1.000 0.919 0.725 0.667 0.544 0.500 0.500 0.459 0.363 0.333 0.250 0.250 0.230 0.167 0.181 0.167 0.181 FSO/FSI [kHz] 192/48.0 48.0/48.0 44.1/48.0 32.0/44.1 32.0/48.0 48.0/88.2 48.0/96.0 44.1/88.2 44.1/96.0 32.0/88.2 32.0/96.0 48.0/192.0 44.1/176.4 44.1/192.0 32.0/192.0 32.0/176.4 8/48.0 8/44.1 Passband [kHz] 22.000 22.000 20.000 14.088 13.688 19.250 20.900 19.202 18.700 12.863 12.500 17.600 16.170 15.860 11.200 10.278 2.800 2.5695 Stopband [kHz] 26.000 26.000 24.100 17.487 17.488 26.232 27.000 24.806 25.000 18.665 18.900 30.200 27.746 28.240 19.600 17.987 4.900 4.4968 Stopband Attenuation [dB] -121.2 -121.2 -121.4 -115.3 -116.9 -114.6 -100.2 -100.2 -103.3 -102.0 -103.6 -104.0 -104.0 -103.3 -73.2 -73.2 -73.2 -73.2 Gain [dB] -0.01@ 20k -0.01@ 20k -0.01@ 20k -0.01@ 14.5k -0.19@ 14.5k -0.03@ 20k -0.01@ 20k -0.08@ 20k -0.23@ 20k -0.75@ 14.5k -1.07@ 14.5k -0.18@ 20k -1.34@ 20k -1.40@ 20k -2.97@ 14.5k -7.88@ 14.5k -2.97@ 3.625k -7.88@ 3.625k
Table 8. Digital Filter Example
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[AK4125]
PACKAGE
30pin VSOP (Unit: mm)
*9.70.1 0.3 30 1.5MAX
16 A 7.60.2 0.15 +0.10 -0.05 Detail A 0.450.2
1 0.220.1
15 0.65
0.12 M
1.20.10
0.08
NOTE: Dimension "*" does not include mold flash.
Material & Lead finish
Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder (Pb free) plate
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0.10 -0.05
+0.10
5.60.1
2007/07
[AK4125]
MARKING
AKM AK4125VF XXXBYYYYC
XXXBYYYYC
Date code identifier
XXXB: Lot number (X: Digit number, B: Alpha character) YYYYC: Assembly date (Y: Digit number, C: Alpha character)
REVISION HISTORY
Date (YY/MM/DD) 05/01/05 05/05/10 06/06/20 07/02/20 07/07/25 Revision 00 01 02 03 04 Reason First Edition Comment Addition Error Correction Error Correction Description Change Page 22 6 9 20,21 16 18 Contents A note on IBICK was added. THD+N Worst Case condition FSO/FSI = 48kHz/8kHz 32kHz/176.4kHz Switching Characteristics (ILRCK) Master/Slave modes were added to Duty Cycle. Connections of PLL1/PLL0 pins were corrected. Figure 9 and Figure 10 were changed. Internal Rest Function for Clock Change Sequence of Changing Clocks UNLOCK pin
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[AK4125]
IMPORTANT NOTICE These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification.
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